A New Metastability Immune Warning Detection Using Edge Detector and Resilient Circuit

In this paper, a new metastability immune warning detection flipflop (FF) is proposed, which consists of an edge detector, a warning window creator, and a caution detector along with a resilient circuit. The delayed data are monitored during the warning window to flag a warning signal before the data enter the erroneous zone. In this scheme, the warning window is self-governing of input clock frequency and hence is suitable for frequency scaling application. A resilient circuit test-chip is implement with timing-error detection and recovery circuits to eliminate the clock frequency protector band from dynamic supply voltage and temperature variations as well as to exploit pathactivation probability for maximizing throughput. Two error-detection sequential circuits are introduced to preserve the timing-error detection ability of preceding EDS designs while lowering clock energy and removing datapath metastability.